1. Field of Invention
The present invention relates to a wait control method such that the slower-speed host module can cope with the faster-speed slave module in the bidirectional wait control to control the slave module so as to correctly execute data movement and to terminate the movement cycle.
2. Description of Related Art
In a conventional system, when there are two modules (host and slave), for example, the host module is the central processing unit (CPU) and the slave module is the memory, when the host module requests the slave module to move data, it can assert a movement cycle start signal, such as CS#, ADS#, . . . signals to inform the slave module. At this point, since the speed of the host module is higher than that of the slave module, the host module can arbitrarily wait for the slave module to assert a READY signal to respond to the host module. For example, after the READY signal is sent in response to the host module, the data movement cycle is terminated. In the design of this well-known system, this function is limited because only the host module is allowed to wait for the slave module, but not vice versa.
Conversely, when the slave module receives (for example) the movement cycle signal CS#, the slave module can quickly respond to the host module with a prepared READY signal. In other words, when the execution speed of the slave module is higher than the response speed of the host module, a problem will exist, namely, that the host module is not able to receive this READY signal in a normal movement cycle.
For example, in a modularized system the interaction between the host module and the slave module is conducted via a 35 MHz synchronizing interface bus (refer to FIG. 1A), the operating frequency of the host module is 20 MHz, but the operating frequency of the slave module is 33 MHz, which is synchronizing with the frequency of the interface bus. First, the CPU of the host module executes at a speed of 20 MHz. When the host module asserts a CCS# (CPU cycle start signal) intending to read out data from the memory of the slave module, the host module should first convert in a synchronized manner the CCS# into a synchronized HCS# (host cycle start signal) with the 33 MHz interface bus. Then the signal HCS# is sent to the memory (slave module) via the synchronizing interface bus. When the memory (slave module) sends a 33 MHz slave READY signal (SRDY#) indicating the ready state of the readout data to the host module. The host module should convert the SRDY# to a CRDY# such that the 20 MHz CPU can accept it. Thus, a normal wait operation is completed. But a situation may exist in which the slave module speed may be higher than the host module speed.
It is customary to solve the problem of the speed of the memory, the slave module, being higher than the host module CPU speed; for example, generally a latch device in the host module latches the readout data moved from the faster-speed memory (while the CPU reads out data from the memory) until the termination is possible for the readout cycle of the host module CPU, then from the latch device with which the readout data is latched this data is read out to formally terminate this readout cycle.
In the method of solution in which the latch device latches the data in the case when the slave module speed is higher than the host module speed, although this problem of speed disparity between the host and slave modules in moving a single block of data in the data readout cycle of a single CPU can involve latch of data, however, when the memory module applies a pulse train during the movement readout cycle (this is also referred to as the data movement method with a burst cycle), the latch device is unable to effectively latch this continuously emerging data.
In FIG. 1A, for example, in the customary modularized system, the interaction between the 20 MHz host module CPU and the 33 MHz slave module memory is frequency-synchronized through a 33 MHz synchronizing interface bus. However, if in the state with a pulse train burst cycle for readout data as shown in FIG. 1B, a 33 MHz HCS# is asserted after 33 MHz synchronizing conversion of CCS# transmitted by the 20 MHz CPU in the host module; after this HCS# is presented to the slave module from the synchronizing interface bus, data transmission with pulse trains begins. In the situation of not knowing the slower speed of the host module for continuous data movement, such as movement of two data blocks accompanied by two continuous slave-asserted signals SRDY# to notify the host module for data readout, after 20 MHz synchronizing conversion by the host module, the first SRDY# asserts a 20 MHz CRDY# to the 20 MHz CPU. In FIG. 1B, it is clearly at that time that the 20 MHz CRDY# will overlap the 30 MHz second SRDY#. Now, if the above mentioned conventional method of solving the single data block problem is used with a latch device to latch the first data block (D1), then after the readout of the first data block (D1) by the host module CPU, the second data block (D2) continuously generated by the slave module memory will be lost, thus it is unable to latch (for example) the second data block (D2) continuously moved by the block stack.
A purpose of this invention aims to smoothly solve the problem by using a pulse train to read out and move data when the slave module speed is higher than the host module speed.
Another purpose of this invention is to solve the problem of dissimilar termination times of data movement cycles between different speeds of host module and slave module by using a wait control circuit of the host module.
Yet another purpose of this invention is to solve the cycle matching problem in which the speed at which the data is read out from the host module is slower than the speed at which the data is written into the slave module.